ARM SVE vs AVX-512: Scalable Vectors vs Fixed 512-Bit SIMD
Arm SVE and x86 AVX-512 both provide predicated vector execution, but their software contracts differ fundamentally: scalable vector length versus a fixed 512-bit maximum width.
[ The paper behind the name ]
QCEV99 paper
QCEV99 takes its name from the citation shorthand associated with a 1999 computer architecture paper by Francisca Quintana, Jesús Corbal, Roger Espasa and Mateo Valero.
What happens when vector execution is added to a superscalar processor?
The architectural problem
Superscalar processors and vector processors expose parallelism differently.
A superscalar processor examines a stream of scalar instructions and attempts to execute multiple independent operations during the same cycle. A vector architecture allows one instruction to describe the same operation across multiple data elements.
One approach asks hardware to discover parallel work. The other gives software a way to express parallel work more directly. The 1999 research explored what could happen when those ideas were combined rather than treated as completely separate approaches.
Why the question still matters
Modern processors look very different from the machines researchers were studying in the late 1990s, but several underlying constraints remain familiar. Execution width has increased. Memory systems have become more complicated. Compilers have improved. SIMD instruction sets have expanded. Scalable vector architectures have emerged. GPUs and specialized accelerators now dominate many highly parallel workloads.
Yet processor designers still have to decide where complexity belongs. Should hardware discover parallelism dynamically? Should software express parallelism explicitly? How wide should execution resources become? How do you keep them fed with data? How much specialization is worthwhile?
Those are still architecture questions.
Then and now
| 1999 architectural concept | Modern counterpart |
|---|---|
| Superscalar execution | Wide out-of-order CPU cores |
| Vector operations | AVX, SVE, RVV and accelerator execution |
| Explicit data parallelism | SIMD, vectors, GPU kernels and tensor operations |
| Vector memory operations | Wide loads, gather and scatter, scalable vector memory access |
| Hardware and software parallelism tradeoff | Compiler, ISA and microarchitecture co-design |
| Increasing execution width | Wider CPU vectors, GPUs and matrix engines |
Continue from QCEV99
- Superscalar vs vector processors
- SIMD vs vector processing
- ARM SVE explained
- RISC-V Vector explained
- What QCEV99 got right
A note on sourcing
Where bibliographic details, DOI links or quotations from the historical paper appear on this site, they are taken from verified primary sources. QCEV99 does not reproduce portions of the paper beyond short quotation for commentary, and is not affiliated with its authors or their institutions.
Then and now
| 1999 architectural concept | Modern counterpart |
|---|---|
| Superscalar execution | Wide out of order CPU cores |
| Vector operations | AVX, SVE, RVV and accelerator execution |
| Explicit data parallelism | SIMD, vectors, GPU kernels and tensor operations |
| Vector memory operations | Wide loads, gather and scatter, scalable vector memory access |
| Hardware and software parallelism tradeoff | Compiler, ISA and microarchitecture co-design |
| Increasing execution width | Wider CPU vectors, GPUs and matrix engines |
Where bibliographic details, identifiers or quotations from the historical paper are shown, use verified primary sources. Do not reproduce copyrighted portions of the paper beyond short quotations for commentary.
Continue from QCEV99
Gather and scatter instructions
Indexed vector memory access, its cost, and when a data layout change beats it.
Memory aliasing and vectorization
Why the compiler assumes your pointers overlap, and what restrict actually promises.