See what the compiler sees, before reading the assembly
QCEV Vector Inspector helps developers reason about whether performance critical code is suitable for vector execution.
Paste a loop. Choose a target architecture. Inspect the dependencies, memory behavior and operations that may influence vectorization.
"Loop not vectorized" is not an explanation
Automatic vectorization depends on more than whether a loop contains arithmetic. The compiler must reason about dependencies. It must understand whether pointers alias. It must determine whether memory can be accessed efficiently. Control flow may need to be transformed. The target processor needs appropriate instructions. And sometimes vectorization is possible but still not profitable.
Vector Inspector organizes those questions into an architecture focused analysis that humans can understand.
From source code to architectural questions
Paste a compact C, C++, Rust-like or pseudocode loop that represents the hot part of your workload.
Select the execution model you want to investigate: generic SIMD, x86 AVX2, x86 AVX-512, ARM NEON, ARM SVE or RISC-V Vector.
Iteration dependencies, memory access patterns, branching, reductions, likely vector operations, possible blockers and architecture specific considerations.
Use the analysis as a starting point, then confirm with compiler optimization reports, generated assembly, hardware profiling and realistic benchmarks.
Example
for (int i = 0; i < n; ++i) {
out[i] = x[i] * a + y[i];
}
Each loop iteration appears independent. The primary memory accesses are sequential. The arithmetic consists of operations that commonly map to vector instructions.
Confirm that out, x and y do not alias in ways that prevent optimization. Inspect the compiler optimization report. Benchmark the generated code on the target processor.
AVX2 may process multiple floating point values per instruction using fixed width vector registers. AVX-512 can operate on wider vectors and provides richer masking functionality. ARM SVE allows software to express this operation without assuming one fixed implementation vector width. RISC-V Vector similarly supports vector length agnostic execution patterns.
An analysis tool, not a benchmark oracle
Vector Inspector does not replace your compiler. It does not replace a profiler. It cannot determine the exact performance of code without knowing the complete program, compiler, flags, runtime inputs and physical processor. Its purpose is different: it helps you ask better performance questions before you descend into the assembly.
Vectorization readiness
Quickly identify whether a loop appears structurally suitable for data parallel execution.
Dependency explanations
Understand loop carried dependencies, reductions and other relationships between iterations.
Memory pattern inspection
Reason about sequential, strided and indirect memory access.
ISA perspective
Compare how the same conceptual workload relates to major vector and SIMD architectures.
Suggested investigation
Practical next steps such as checking aliasing assumptions, compiler reports or generated instructions.
Learn while optimizing
Every recommendation teaches the architectural principle behind it.
“Loop not vectorized” is not an explanation
Automatic vectorization depends on more than whether a loop contains arithmetic. The compiler must reason about dependencies. It must understand whether pointers alias. It must determine whether memory can be accessed efficiently. Control flow may need to be transformed. The target processor needs appropriate instructions. And sometimes vectorization is possible but still not profitable.
Vector Inspector organizes those questions into an architecture-focused analysis that humans can understand.
From source code to architectural questions
1. Add your kernel
Paste a compact C, C++, Rust-like or pseudocode loop that represents the hot part of your workload.
2. Choose an architecture
- Generic SIMD
- x86 AVX2
- x86 AVX-512
- ARM NEON
- ARM SVE
- RISC-V Vector
3. Inspect the analysis
- potential iteration dependencies
- memory access patterns
- branching
- reductions
- likely vector operations
- possible blockers
- architecture-specific considerations
4. Validate on real hardware
Use the analysis as a starting point, then confirm with compiler optimization reports, generated assembly, hardware profiling and realistic benchmarks.
Example
for (int i = 0; i < n; ++i) {
out[i] = x[i] * a + y[i];
}Vectorization potential: high
Each loop iteration appears independent. The primary memory accesses are sequential. The arithmetic consists of operations that commonly map to vector instructions.
Possible vector operations
- load vector x
- broadcast scalar a
- multiply
- load vector y
- add
- store vector out
Architecture notes
AVX2 may process multiple floating-point values per instruction using fixed-width vector registers. AVX-512 can operate on wider vectors and provides richer masking functionality. ARM SVE allows software to express this operation without assuming one fixed implementation vector width. RISC-V Vector similarly supports vector-length agnostic execution patterns.
Next checks
- Confirm that
out,xandydo not alias in ways that prevent optimization. - Inspect the compiler’s optimization report.
- Benchmark the generated code on the target processor.
An analysis tool, not a benchmark oracle
Vector Inspector does not replace your compiler. It does not replace a profiler. It cannot determine the exact performance of code without knowing the complete program, compiler, flags, runtime inputs and physical processor.
Its purpose is different. Vector Inspector helps you ask better performance questions before you descend into the assembly.
Features
Vectorization readiness
Quickly identify whether a loop appears structurally suitable for data-parallel execution.
Dependency explanations
Understand loop-carried dependencies, reductions and other relationships between iterations.
Memory pattern inspection
Reason about sequential, strided and indirect memory access.
ISA perspective
Compare how the same conceptual workload relates to major vector and SIMD architectures.
Suggested investigation
Receive practical next steps such as checking aliasing assumptions, compiler reports or generated instructions.
Learn while optimizing
Every recommendation explains the architectural principle behind it.
Questions
Does Vector Inspector compile my code?
Not necessarily. Vector Inspector focuses on architectural analysis and vectorization reasoning. Compiler output should still be treated as the authoritative source for what a particular compiler actually generates.
Can it tell me exactly how fast my code will run?
No. Real performance depends on the processor, compiler, optimization flags, surrounding code, memory hierarchy, data size, runtime behavior and many other factors. Vector Inspector helps identify architectural opportunities and potential blockers.
Does it replace Compiler Explorer?
No. They solve different problems. Compiler Explorer is excellent for examining generated compiler output. Vector Inspector focuses on explaining the vectorization and architectural questions surrounding a kernel. They work well together.
Which architectures are covered?
The product is designed around generic vector principles and major contemporary models including AVX2, AVX-512, ARM NEON, ARM SVE and RISC-V Vector. Specific capabilities may vary during Early Access.
Can students use it?
Yes. Teaching architecture is one of the reasons QCEV99 exists.
Is uploaded code private?
See our Privacy Policy for details about how submitted data is processed and retained.