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RISC-V

The RISC-V Vector extension, vector-length agnostic programming and emerging hardware.

All Vector architecture ARM x86 CPU microarchitecture Foundations Compilers Performance Engineering RISC-V SIMD GPUs and accelerators Architecture history

RISC-V4 Oct 20264 min

RISC-V Vector vs ARM SVE

Two length-agnostic architectures compared: register grouping, predication and memory operations.

RISC-V22 Aug 20262 min

RISC-V Vector explained

Understanding vector length, LMUL, masking and vector-length agnostic execution in the RISC-V “V” extension.

RISC-V11 Aug 20264 min

RISC-V Vector Explained: VLEN, VL, SEW and LMUL

A practical introduction to the RISC-V V vector extension: vector registers, VLEN, active vector length, SEW, LMUL, masks and portable strip-mined loops.

RISC-V

RISC-V Vector vs ARM SVE

RISC-V Vector explained

RISC-V Vector Explained: VLEN, VL, SEW and LMUL

One architecture idea at a time