Vector reductions explained
Horizontal operations, floating-point reassociation and the cost of the final combine.
Research
Processor architecture becomes easier to understand when individual mechanisms are connected to the larger problem they are trying to solve.
ARM SVE vs AVX-512: Scalable Vectors vs Fixed 512-Bit SIMD
Arm SVE and x86 AVX-512 both provide predicated vector execution, but their software contracts differ fundamentally: scalable vector length versus a fixed 512-bit maximum width.
Gather and scatter instructions
Indexed vector memory access, its cost, and when a data layout change beats it.
Memory aliasing and vectorization
Why the compiler assumes your pointers overlap, and what restrict actually promises.
Loop-carried dependencies explained
Dependency distance, recurrences, reductions and which patterns a compiler can still vectorize.
Superscalar vs Vector Architecture
Superscalar cores discover independent scalar instructions dynamically; vector architectures let software state data parallelism explicitly. Modern CPUs combine both ideas.
AVX2 vs AVX-512
Width, masking, frequency behavior and how to decide which to target.
NEON vs SVE
Fixed 128-bit SIMD against scalable vectors on the same architecture family.
RISC-V Vector vs ARM SVE
Two length-agnostic architectures compared: register grouping, predication and memory operations.
ARM SVE explained
Scalable vectors, predication and vector-length agnostic software on ARM.
Understand the code behind the architecture
QCEV Vector Inspector helps you reason about vectorization opportunities, memory access and dependencies in performance critical loops.