Architecture guides
Start with the fundamentals and work toward modern vector and processor architectures. These guides explain both what a mechanism does and why the architecture needs it.
Start with the fundamentals and work toward modern vector and processor architectures.
Whether you are a student, systems programmer or performance engineer, these guides are designed to explain both what a mechanism does and why the architecture needs it.
Start here
- What is instruction-level parallelism?
- What is a superscalar processor?
- What is SIMD?
- What is a vector processor?
- SIMD vs vector processing
- CPU vs GPU execution models
Modern vector architectures
- AVX2 explained
- AVX-512 explained
- ARM NEON explained
- ARM SVE explained
- RISC-V Vector explained
- Vector-length agnostic programming
CPU microarchitecture
- Out-of-order execution
- Register renaming
- Branch prediction
- Reorder buffers
- Execution ports
- Cache hierarchies
- Memory-level parallelism
Performance engineering
- Why compilers fail to vectorize loops
- Understanding compiler vectorization reports
- Loop-carried dependencies
- Memory aliasing
- Alignment and SIMD
- Gather and scatter
- Vector reductions
- When SIMD makes code slower
- ARM NEON explained
- ARM SVE explained
- ARM SVE Explained: Scalable Vectors and Predication
- ARM SVE vs AVX-512
- NEON vs SVE
- NEON vs SVE: Fixed 128-Bit SIMD vs Scalable Vectors
- Loop-carried dependencies explained
- Memory aliasing and vectorization
- Why compilers fail to vectorize loops
- Why Compilers Fail to Vectorize Loops
- How Event Pipelines Move from CPU Counters to Application Analytics
- Superscalar vs vector architecture
- Superscalar vs vector processors
- What is a superscalar processor?
- What is instruction-level parallelism?
- SIMD vs Vector Processing: What Is the Difference?
- Superscalar vs Vector Architecture
- What Is a Superscalar Processor?
- What Is a Vector Processor?
- What Is Instruction-Level Parallelism?
- Gather and Scatter Instructions Explained
- How Event Pipelines Move from CPU Counters to Application Analytics
- Loop-Carried Dependencies Explained
- Memory Aliasing and Vectorization
Understand the code behind the architecture
QCEV Vector Inspector helps you reason about vectorization opportunities, memory access and dependencies in performance critical loops.