SIMD vs vector processing

Packed SIMD and vector processing both apply one operation to many data elements. The difference is where the element count lives.

Fixed-width SIMD

In SSE, AVX2, AVX-512 and NEON the register width is part of the architecture. A 256-bit AVX2 register holds eight 32-bit floats, and code written for it encodes that eight. Change the width and you change the instruction set: new registers, new mnemonics, new intrinsics, and usually a new build of the same kernel.

// AVX2: the width 8 is baked into the source
for (int i = 0; i + 8 <= n; i += 8) {
    __m256 vx = _mm256_loadu_ps(&x[i]);
    __m256 vy = _mm256_loadu_ps(&y[i]);
    _mm256_storeu_ps(&out[i], _mm256_add_ps(vx, vy));
}
// plus a scalar tail for the remaining n % 8 elements

Vector-length agnostic execution

Classical vector machines, and modern ARM SVE and RISC-V Vector, treat the length as a runtime property. Software asks the hardware how many elements it will process this iteration and advances by that amount. The same binary runs on a narrow implementation and a wide one.

// RISC-V Vector: the hardware decides the length
for (size_t i = 0; i < n; ) {
    size_t vl = __riscv_vsetvl_e32m1(n - i);
    vfloat32m1_t vx = __riscv_vle32_v_f32m1(&x[i], vl);
    vfloat32m1_t vy = __riscv_vle32_v_f32m1(&y[i], vl);
    __riscv_vse32_v_f32m1(&out[i], __riscv_vfadd_vv_f32m1(vx, vy, vl), vl);
    i += vl;
}

The loop tail disappears with it. The final iteration simply requests fewer elements, rather than falling back to scalar code.

What else tends to travel with each model

The width distinction pulls other features along with it. Length-agnostic designs need active-element masking as a first-class mechanism, since partial vectors are the normal case rather than an edge case. They typically expose loop predication, and RISC-V Vector adds register grouping so several registers can be treated as one longer vector.

Fixed-width SIMD gained comparable capabilities over time: AVX-512 introduced dedicated mask registers, and both families support gather and scatter for indirect access. The result is that the two models have converged in capability while remaining different in software strategy.

The practical distinction

Ask what happens when the hardware gets wider. If your source has to change, you are writing packed SIMD. If the same binary uses the extra lanes, you are writing vector code. Everything else is a detail of the instruction set.

Related tool: QCEV Vector Inspector examines a loop for dependencies, memory access patterns and likely vector operations.

References

• Intel 64 and IA-32 Architectures Software Developer’s Manual, AVX and AVX-512 chapters.
• Arm Architecture Reference Manual, SVE sections; Arm SVE Programming Examples.
• RISC-V “V” Vector Extension specification, RISC-V International.