RISC-V Vector explained

The RISC-V Vector extension, RVV, defines vector execution without fixing a vector register width in the architecture. Software queries the hardware, receives a length, and processes that many elements.

The state that matters

RVV adds 32 vector registers and a small set of control state. Three pieces of it explain most of the programming model:

• VLEN — the implementation’s vector register width in bits. Fixed in hardware, not in the instruction encoding.
• SEW — selected element width: how many bits each element occupies, so how many elements a register holds.
• LMUL — length multiplier: how many vector registers are grouped and treated as one longer vector.

Together these determine vl, the number of elements the next vector instruction will actually process.

The stripmine loop

Instead of incrementing by a constant, an RVV loop asks for a length each iteration and advances by whatever it is granted.

for (size_t i = 0; i < n; ) {
    size_t vl = __riscv_vsetvl_e32m1(n - i);   // SEW=32, LMUL=1
    vfloat32m1_t vx = __riscv_vle32_v_f32m1(&x[i], vl);
    vfloat32m1_t vy = __riscv_vle32_v_f32m1(&y[i], vl);
    vfloat32m1_t vr = __riscv_vfadd_vv_f32m1(vx, vy, vl);
    __riscv_vse32_v_f32m1(&out[i], vr, vl);
    i += vl;
}

On the final iteration the request is smaller than the register can hold and the hardware sets vl accordingly. There is no scalar remainder loop, and the same object code runs on a narrow implementation and a wide one.

What LMUL buys and costs

Raising LMUL groups registers, producing longer vectors and fewer loop iterations, which helps amortise loop overhead on short-vector implementations. The cost is register pressure: at LMUL=8 the register file provides only four independent groups, so a kernel needing many live vectors will spill.

Masking and memory

Most instructions accept a mask so inactive elements are left alone, which is how conditional code inside a loop body becomes vector code. For memory, RVV distinguishes unit-stride, constant-stride and indexed access, plus segment loads and stores that de-interleave structures on the fly. That last group is useful precisely where array-of-structures data would otherwise force a gather.

Where it stands

RVV 1.0 is ratified, and toolchain support in GCC and LLVM has matured alongside a growing set of implementations at very different vector widths. Because the architecture leaves width open, performance portability is a real question: the same binary is correct everywhere, and still wants measuring on each part. Consult the ratified specification for exact instruction behavior rather than relying on summaries.

Related tool: QCEV Vector Inspector examines a loop for dependencies, memory access patterns and likely vector operations.

References

• RISC-V “V” Vector Extension specification, version 1.0, RISC-V International.
• RISC-V Vector C intrinsics specification.
• GCC and LLVM RISC-V vector backend documentation.