RISC-V Vector Explained: VLEN, VL, SEW and LMUL

The RISC-V V vector extension adds a general data-parallel execution model to the RISC-V ISA. Its defining feature is not simply “wide registers.” The architecture separates implementation capacity from the number and type of elements active in a particular operation.

That makes terms such as VLEN, vl, SEW and LMUL central to understanding RVV.

The vector register file

The V extension adds 32 architectural vector registers, v0 through v31. Each register contains VLEN bits of state. VLEN is chosen by the implementation subject to the specification’s constraints.

Software should not automatically equate VLEN with the amount of useful work completed per cycle. An implementation can internally execute vector instructions using its own datapath organization.

VLEN versus vl

VLEN is the architectural size of one vector register in bits for a given implementation.

vl is the current active vector length: the number of elements on which a vector instruction operates.

This separation is what lets a program process an application vector in chunks that fit the current machine.

SEW: selected element width

Vector operations need to know the width of each element. The selected element width, commonly discussed as SEW, can represent byte, halfword, word, doubleword and other supported element sizes depending on the extension and operation.

Smaller elements mean more elements fit into a given amount of vector register state.

LMUL: grouping vector registers

LMUL controls vector register grouping. An operation can use a group representing a fraction, one or multiple vector registers depending on the supported configuration.

A larger LMUL increases the effective register group capacity for a logical vector but consumes more of the architectural register file per value. That creates a tradeoff between elements per group and the number of independent vector groups available.

VLMAX

The maximum element count for the current configuration depends on VLEN, SEW and LMUL. A useful conceptual relationship is:

VLMAX ∝ (VLEN / SEW) × LMUL

The exact architectural rules include allowed fractional and integer LMUL values and constraints defined by the specification.

Strip mining with vsetvli

One of the characteristic RVV patterns is to process a long array in architecture-sized chunks:

remaining = n;
while (remaining > 0) {
    vl = set_vector_length(remaining);
    // load vl elements
    // compute vl elements
    // store vl elements
    remaining -= vl;
}

Real code uses configuration instructions such as vsetvli, vsetivli or vsetvl. The architecture chooses a legal vl and records the active configuration.

This pattern makes the final short chunk part of the ordinary loop rather than requiring a fixed scalar epilogue.

Masks and inactive elements

RVV supports vector masks so operations can selectively affect elements. Masks are important for conditional execution, tails and algorithms in which not every element should commit a result.

The specification also defines policies governing what happens to tail and masked-off elements, which matters when writing low-level code that depends on register contents.

Memory operations

The vector extension includes unit-stride loads/stores, strided forms and indexed forms. Indexed memory operations provide gather/scatter-style behavior for irregular access patterns.

Having an instruction does not make an access pattern cheap. Indexed accesses can still be limited by cache behavior, memory-level parallelism and implementation details.

Reductions and permutations

RVV includes reduction instructions that combine elements toward scalar-like results, plus permutation operations for rearranging vector data. These are crucial because real vector code needs more than element-wise arithmetic.

The V extension and Zve extensions

The RISC-V specification also defines smaller Zve vector extensions intended for embedded use, with different element-width and floating-point capabilities. The single-letter V extension targets application processors and depends on specified vector capabilities including a minimum vector length profile.

C intrinsics

RISC-V International ratified version 1.0 of the Vector C Intrinsic Specification in 2025. It defines the <riscv_vector.h> interface and intrinsic naming/programming conventions for direct RVV use.

For many applications, however, the first choice should still be ordinary code plus compiler auto-vectorization where it produces suitable results. Intrinsics are most valuable when precise operations or data movement need to be expressed.

What makes RVV distinctive?

RVV combines vector-length-agnostic execution with configurable element widths and register grouping. That gives implementers considerable freedom while providing software a standardized way to express long data-parallel loops.

Key takeaways

• RVV adds 32 architectural vector registers.
• VLEN is implementation capacity; vl is the current active element count.
• SEW and LMUL control element size and effective register grouping.
• The normal programming model supports strip mining instead of hard-coding one lane count.
• RVV includes masks, reductions, permutation and multiple memory-access forms.

References and further reading

• RISC-V “V” Vector Extension, Version 1.0
• RISC-V Vector C Intrinsic Specification v1.0

Continue learning

• What Is Vector-Length Agnostic Programming?
• RISC-V Vector vs ARM SVE
• Gather and Scatter Instructions Explained