ARM SVE vs AVX-512: Scalable Vectors vs Fixed 512-Bit SIMD
Arm SVE and x86 AVX-512 both provide predicated vector execution, but their software contracts differ fundamentally: scalable vector length versus a fixed 512-bit maximum width.
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SIMD
Gather and Scatter Instructions Explained
Gather and scatter let vector code load or store elements at non-contiguous indexed addresses. They expand what can be vectorized, but irregular memory remains expensive.
AVX2 vs AVX-512: Width Is Only Part of the Story
AVX-512 doubles maximum vector width over AVX2 and adds masking plus a richer register model, but the fastest choice depends on instruction mix, CPU implementation and memory behavior.
NEON vs SVE: Fixed 128-Bit SIMD vs Scalable Vectors
Arm NEON and SVE both provide data-parallel execution, but NEON exposes fixed 128-bit vectors while SVE is built for scalable, predicated vector-length-agnostic code.
AVX-512 Explained: Wider Vectors, Masks and More Registers
AVX-512 is more than 512-bit arithmetic. Its major architectural changes include opmask predication, a larger vector register file in 64-bit mode and a family of optional feature subsets.
AVX2 Explained: 256-Bit SIMD on x86
AVX2 extends x86 packed SIMD with broad 256-bit integer support and other useful operations. Learn what it adds, where it helps and where its limits begin.
RISC-V Vector Explained: VLEN, VL, SEW and LMUL
A practical introduction to the RISC-V V vector extension: vector registers, VLEN, active vector length, SEW, LMUL, masks and portable strip-mined loops.
Why Compilers Fail to Vectorize Loops
Compilers skip vectorization when legality, profitability or target constraints get in the way. Learn the most common blockers: dependencies, aliasing, control flow, calls and memory access.
SIMD vs Vector Processing: What Is the Difference?
SIMD and vector processing overlap, but they are not always interchangeable terms. This guide separates fixed-width packed SIMD from richer vector-length-based execution models.
What Is a Vector Processor?
A vector processor applies one operation across many data elements using vector registers and vector instructions. Here is how the model works and why it still matters.