RISC-V Vector and Arm SVE both support vector-length-agnostic software, but they expose that capability differently through vl/configuration versus predicates and scalable vector types.
A practical introduction to the RISC-V V vector extension: vector registers, VLEN, active vector length, SEW, LMUL, masks and portable strip-mined loops.
One architecture idea at a time
The QCEV99 Brief is a concise email about processor architecture, vector computing and performance engineering.