What QCEV99 got right
Revisiting a 1999 processor-architecture question in the era of scalable vectors and AI accelerators.
Research
Processor architecture becomes easier to understand when individual mechanisms are connected to the larger problem they are trying to solve.
RISC-V Vector explained
Understanding vector length, LMUL, masking and vector-length agnostic execution in the RISC-V “V” extension.
ARM SVE vs AVX-512
Two approaches to wide vector execution with very different software models: one fixes the register width in the architecture, the other refuses to.
Why compilers fail to vectorize loops
Dependencies, aliasing, alignment, control flow and profitability. The reasons automatic vectorization breaks down, and what each one looks like in source code.
SIMD vs vector processing
They are often treated as synonyms. Fixed-width packed SIMD and vector-length agnostic vector execution differ in the one place that matters most to software: whether the width is in your binary.
Superscalar vs vector processors
Two very different approaches to extracting parallel work from an instruction stream: one discovers parallelism in hardware, the other lets software describe it.
Gather and Scatter Instructions Explained
Gather and scatter let vector code load or store elements at non-contiguous indexed addresses. They expand what can be vectorized, but irregular memory remains expensive.
Memory Aliasing and Vectorization
When two pointers may refer to overlapping storage, a compiler can be forced to preserve scalar ordering. Learn how alias analysis, restrict and runtime checks affect vectorization.
Loop-Carried Dependencies Explained
A loop-carried dependency connects one iteration to another. It is one of the most important reasons a loop cannot be executed or vectorized as independent iterations.
AVX2 vs AVX-512: Width Is Only Part of the Story
AVX-512 doubles maximum vector width over AVX2 and adds masking plus a richer register model, but the fastest choice depends on instruction mix, CPU implementation and memory behavior.
Understand the code behind the architecture
QCEV Vector Inspector helps you reason about vectorization opportunities, memory access and dependencies in performance critical loops.