ARM NEON explained
The 128-bit ARM SIMD baseline: registers, intrinsics and what it does and does not provide.
Research
Processor architecture becomes easier to understand when individual mechanisms are connected to the larger problem they are trying to solve.
AVX-512 explained
Wider registers, mask registers, embedded rounding, and the subset and deployment complications.
AVX2 explained
256-bit registers, the integer instructions AVX lacked, gather, and where AVX2 still sits as a safe x86 baseline.
What is vector-length agnostic programming?
Writing one kernel that uses whatever vector width the hardware provides.
What is vector length?
Vector length, element width and the difference between what a register holds and what an instruction processes.
How Event Pipelines Move from CPU Counters to Application Analytics
A practical bridge from hardware performance counters to application analytics: how high-volume systems collect raw events, normalize them, detect anomalies, and turn noisy measurements into useful debugging and reporting signals.
What is instruction-level parallelism?
Independent instructions in a sequential stream, and the limits on how many of them hardware can find.
Superscalar vs vector architecture
A design-level comparison of the two ways a processor can get more work out of a cycle.
What is a superscalar processor?
Multiple instructions per cycle, and the renaming, scheduling and retirement machinery that makes it safe.
What is a vector processor?
One instruction, many elements: vector registers, vector length and why describing parallelism beats discovering it.
Understand the code behind the architecture
QCEV Vector Inspector helps you reason about vectorization opportunities, memory access and dependencies in performance critical loops.