NEON vs SVE: Fixed 128-Bit SIMD vs Scalable Vectors
Arm NEON and SVE both provide data-parallel execution, but NEON exposes fixed 128-bit vectors while SVE is built for scalable, predicated vector-length-agnostic code.
Research
Processor architecture becomes easier to understand when individual mechanisms are connected to the larger problem they are trying to solve.
RISC-V Vector vs ARM SVE: Two Scalable Vector Models
RISC-V Vector and Arm SVE both support vector-length-agnostic software, but they expose that capability differently through vl/configuration versus predicates and scalable vector types.
AVX-512 Explained: Wider Vectors, Masks and More Registers
AVX-512 is more than 512-bit arithmetic. Its major architectural changes include opmask predication, a larger vector register file in 64-bit mode and a family of optional feature subsets.
AVX2 Explained: 256-Bit SIMD on x86
AVX2 extends x86 packed SIMD with broad 256-bit integer support and other useful operations. Learn what it adds, where it helps and where its limits begin.
ARM SVE Explained: Scalable Vectors and Predication
Arm SVE is a scalable vector architecture built around implementation-defined vector length and pervasive predication. Learn the model, loop style and why it differs from NEON.
RISC-V Vector Explained: VLEN, VL, SEW and LMUL
A practical introduction to the RISC-V V vector extension: vector registers, VLEN, active vector length, SEW, LMUL, masks and portable strip-mined loops.
What Is Vector-Length Agnostic Programming?
Vector-length agnostic code avoids assuming one hardware vector width. Instead it progresses according to the active elements available on the current implementation.
What Is Vector Length?
Vector length can mean register capacity, active elements or a software vectorization factor. Distinguishing those meanings is essential when comparing AVX, SVE and RISC-V Vector.
Why Compilers Fail to Vectorize Loops
Compilers skip vectorization when legality, profitability or target constraints get in the way. Learn the most common blockers: dependencies, aliasing, control flow, calls and memory access.
What Is Instruction-Level Parallelism?
Instruction-level parallelism is the amount of independent work available among instructions in one thread. It is the raw material used by superscalar and out-of-order CPUs.
Understand the code behind the architecture
QCEV Vector Inspector helps you reason about vectorization opportunities, memory access and dependencies in performance critical loops.